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freescale semiconductor, inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc33886 rev 8.0, 2/2007 freescale semiconductor technical data ? freescale semiconductor, in c., 2007. all rights reserved. 5.0 a h-bridge the 33886 is a monolithic h-bridge ideal for fractional horsepower dc-motor and bi-directional thrust solenoid control. the ic incorporates internal control logic, charge pump, gate drive, and low r ds(on) mosfet output circuitry. the 33886 is able to control continuous inductive dc load currents up to 5.0 a. output loads can be pulse width modulated (pwm-ed) at frequencies up to 10 khz. a fault status output reports u ndervoltage, short circuit, and overtemperature conditions. two independent inputs control the two half-bridge totem-pole outputs. two disable inputs force the h-bridge outputs to tri-state (exhibit high impedance). the 33886 is parametrically specif ied over a temper ature range of -40 c t a 125 c, 5.0 v v+ 28 v. the ic can also be operated up to 40 v with derating of the specifications. the ic is available in a surface mount power package with exposed pad for heatsinking. features ?5.0 v to 40 v continuous operation ?120 m ? r ds(on) h-bridge mosfets ?ttl / cmos compatible inputs ? pwm frequencies up to 10 khz ? active current limiting via internal constant off-time pwm (with temperature-dependent threshold reduction) ? output short circuit protection ? undervoltage shutdown ? fault status reporting ? pb-free packaging designated by suffix code vw figure 1. 33886 simplified application diagram h-bridge vw suffix (pb-free) dh suffix 98ash70702a 20-pin hsop 33886 ordering information device temperature range (t a ) package mc33886dh/r2 - 40c to 125c 20 hsop MC33886VW/r2 5.0 v motor mcu out2 out1 v+ c cp agnd fs in1 d1 in2 d2 33886 in out out out out pgnd v+
analog integrated circuit device data 2 freescale semiconductor 33886 internal block diagram internal block diagram figure 2. 33886 simplifi ed internal block diagram charge pump over- temperature 5.0 v regulator gate drive cur rent li mit, overcurrent sense ci rc uit undervoltage out1 out2 in1 in2 d1 d2 fs c cp v pwr pgnd agnd control logic 80 ua (each) 25 ua 80 a 25 a current limit, short circuit sense circuit charge pump 5.0 v regulator gate drive over- temperature undervoltage v+ ccp
analog integrated circuit device data freescale semiconductor 3 33886 pin connections pin connections figure 3. 33886 pin connections table 1. 33886 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 15 . pin number pin name formal name definition 1 agnd analog ground low-current analog signal ground. 2 fs fault status for h- bridge open drain active low fault status output requiring a pull-up resistor to 5.0 v. 3 in1 logic input control 1 true logic input control of out1 (i .e., in1 logic high = out1 logic high). 4, 5, 16 v + positive power supply positive supply connections. 6, 7 out1 h-bridge output 1 output 1 of h-bridge. 8, 20 dnc do not connect either do not connect (leave floating) or connect these pins to ground in the application. they are test mode pins used in manufacturing only. 9 ?12 pgnd power ground device high-current power ground. 13 d2 disable 2 active low input used to simultaneously tr i-state disable both h-bridge outputs. when d2 is logic low, both outputs are tri-stated. 14, 15 out2 h-bridge output 2 output 2 of h-bridge. 17 ccp charge pump capacitor external reservoir capacitor connecti on for internal charge pump capacitor. 18 d1 disable 1 active high input used to simultaneously tri-state disable both h-bridge outputs. when d1 is logic high, both outputs are tri-stated. 19 in2 logic input control 2 true logic input control of out2 (i .e., in2 logic high = out2 logic high). dnc agnd in2 d1 ccp v+ out2 out2 d2 pgnd pgnd fs v+ out1 out1 dnc pgnd pgnd in1 v+ 1 2 3 4 5 6 7 8 9 10 20 19 16 15 14 13 12 11 18 17
analog integrated circuit device data 4 freescale semiconductor 33886 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol value unit supply voltage v+ 40 v input voltage (1) v in -0.1 to 7.0 v fs status output (2) v fs 7.0 v continuous current (3) i out 5.0 a esd voltage for dh package human body model (4) machine model (5) v esd1 v esd2 2000 (6) 200 v esd voltage for vw package human body model (4) machine model (5) v esd1 v esd2 2000 200 v storage temperature t stg -65 to 150 c ambient operating temperature (7) t a -40 to 125 c operating junction temperature t j -40 to 150 c peak package reflow temperature during reflow (8) , (9) t pprt note 8. c approximate junction-to-board thermal resistance (and package dissipation = 6.0 w) (10) r jb ~5.0 c/w notes 1. exceeding the input voltage on in1, in2, d1, or d2 may cause a malfunction or permanent damage to the device. 2. exceeding the pull-up resistor voltage on the open drain fs pin may cause permanent damage to the device. 3. continuous current capability so lo ng as junction temperature is 150 c. 4. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 5. esd2 testing is performed in ac cordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 6. all pins are capable of human body model esd voltages of 2000 v with two exceptions pertaining only to the dh suffix package: (1) d2 to pgnd is capable of 1500 v and (2) out1 to agnd is capable of 1000 v. 7. the limiting factor is junction temperat ure, taking into account the power dissipat ion, thermal resistance, and heatsinking. 8. pin soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 9. freescale?s package reflow capability meets pb-free requirem ents for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove prefix es/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. 10. exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. the actual r jb (junction-to-pc board) values will vary depending on solder thickness and composition and copper trace.
analog integrated circuit device data freescale semiconductor 5 33886 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power supply operating voltage range (11) v+ 5.0 ? 40 v standby supply current v en = 5.0 v, i out = 0 a i q (standby) ? ? 20 ma threshold supply voltage switch-off switch-on hysteresis v+ (thres-off) v+ (thres-on) v+ (hys) 4.15 4.5 150 4.4 4.75 ? 4.65 5.0 ? v v mv charge pump charge pump voltage v+ = 5.0 v 8.0 v v+ 40 v v cp - v+ 3.35 ? ? ? ? 20 v control inputs input voltage (in1, in2, d1, d2 ) threshold high threshold low hysteresis v ih v il v hys 3.5 ? 0.7 ? ? 1.0 ? 1.4 ? v input current (in1, in2, d1) (12) v in = 0 v i in -200 -80 ? a d2 input current (13) v d2 = 5.0 v i d2 ? 25 100 a notes 11. specifications are characterized over the range of 5.0 v v+ 28 v. operation > 28 v will cause some parameters to exceed listed min/max values. refer to typical operating cu rves to extrapolate values for operation > 28 v but 40 v. 12. inputs in1, in2, and d1 have independent internal pull-up current sources. 13. the d2 input incorporates an active internal pull-down current sink.
analog integrated circuit device data 6 freescale semiconductor 33886 electrical characteristics static electrical characteristics power outputs (out1, out2) output-on resistance (14) 5.0 v v+ 28 v, t j = 25c 8.0 v v+ 28 v, t j = 150c 5.0 v v+ 8.0 v, t j = 150c r ds(on) ? ? ? 120 ? ? ? 225 300 m ? active current limiting threshold (via internal constant off-time pwm) (15) i lim 5.2 6.5 7.8 a high-side short circuit detection threshold i sch 11 ? ? a low-side short circuit detection threshold i scl 8.0 ? ? a leakage current (16) v out = v+ v out = gnd i out(leak) ? ? 100 30 200 60 a output fet body diode forward voltage drop (17) i out = 3.0 a v f ? ? 2.0 v switch-off thermal shutdown hysteresis t lim t hys 175 ? ? 15 ? ? c fault status (18) fault status leakage current (19) v fs = 5.0 v i fs (leak) ? ? 10 a fault status set voltage (20) i fs = 300 a v fs (low) ? ? 1.0 v notes 14. output-on resistance as measured from output to v+ and ground. 15. product with date codes of december 2002, week 51, will exhibit the va lues indicated in this table. product with earlier dat e codes may exhibit a minimum of 6.0 a and a maximum of 8.5 a. 16. outputs switched off with d1 or d2 . 17. parameter is guaranteed by design but not production tested. 18. fault status output is an open drain output requiring a pull-up resistor to 5.0 v. 19. fault status leakage current is measured with fault status high and not set. 20. fault status set voltage is measured with fault status low and set with i fs = 300 a. table 3. static elec trical characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 7 33886 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit timing characteristics pwm frequency (21) f pwm ? ? 10 khz maximum switching frequency during active current limiting (22) f max ? ? 20 khz output on delay (23) v+ = 14 v t d (on) ? ? 18 s output off delay (23) v+ = 14 v t d (off) ? ? 18 s output rise and fall time (24) v+ = 14 v, i out = 3.0 a t f , t r 2.0 5.0 8.0 s output latch-off time t a 15 20.5 26 s output blanking time t b 12 16.5 21 s output fet body diode reverse recovery time (25) t r r 100 ? ? ns disable delay time (26) t d (disable) ? ? 8.0 s short circuit / overtemperature turn- off time (27) t fault ? 4.0 ? s power-off delay time t pod ? 1.0 5.0 ms notes 21. the outputs can be pwm controlled from an external source. this is typically done by holding one input high while applying a pwm pulse train to the other input. the maxi mum pwm frequency obtainable is a compromise between switching losses and switching frequency. refer to typical switching waveforms, figures 10 through 17 , pp. 10? 11 . 22. the maximum switching frequency during active current limiting is internally implem ented. the internal control produces a co nstant off-time pwm of the output. the output load current effects the maximum switching frequency. 23. output delay is the time duration from the midpoint of the in 1 or in2 input signal to the 10% or 90% point (dependent on the transition direction) of the out1 or out2 signal. if the output is transit ioning high-to-low, the delay is from the midpoint of the input signal to the 90% point of the output response signal. if the output is transitio ning low-to-high, the delay is from the midpoint of the inpu t signal to the 10% point of the output response signal. see figure 4 , page 8 . 24. rise time is from the 10% to the 90% level and fall time is from the 90% to the 10% level of the output signal. see figure 6 , page 8 . 25. parameter is guaranteed by design but not production tested. 26. disable delay time is the time duration from the midpoint of the d (disable) input signal to 10% of the output tri-state res ponse. see figure 5 , page 8 . 27. increasing currents will become limited at i lim . hard shorts will breach the i sch or i scl limit, forcing the output into an immediate tri- state latch-off. see figures 8 and 9 , page 9 . active current limiting will cause junction temperatures to rise. a junction temperature above 160 c will cause the active current limi ting to progressively ?fold-back? (o r decrease) to 2.5 a typical at 175 c where thermal latch-off will occur. see figure 7 , page 8 .
analog integrated circuit device data 8 freescale semiconductor 33886 timing diagrams timing diagrams figure 4. output delay time figure 5. disable delay time figure 6. output switching time figure 7. active curre nt limiting versus temperature (typical) time 0 5.0 0 v pwr t d(on) 50% 90% 50% 10% v i n 1 , i n 2 ( v ) t d(off) v o u t 1 , 2 ( v ) ? 0 v 5.0 v 0 ? t r 0 v pwr 90% 10% v o u t 1 , 2 ( v ) 10% 90% t f i m a x , o u t p u t c u r r e n t ( a ) 6.6 2.5 160 175 thermal shutdown t j , junction temperature ( o c) i lim , 6.5 i lim , current (a)
analog integrated circuit device data freescale semiconductor 9 33886 timing diagrams figure 8. active curr ent limiting versus time figure 9. active cu rrent limiting detail d 1 , l o g i c i n [0] [1] hard short detect and latch-off typ. short ckt. detect threshold pwm current limiting (see figure 6) 8.0 6.5 i l o a d , o u t p u t c u r r e n t ( a ) f s , l o g i c o u t ou tp uts tristated t i m e d 2 , l o g i c i n [0] [0] [1] [1] i n n , l o g i c i n [0] [1] in1 in2 in2 in1 out puts operat ional (per input control condition) 0 typ. current limit threshold outputs tristated in2 in1 or or in1 or in2 in2 or in1 diode reverse rec overy spike s (see figure 7) i scl short circuit detect threshold for low-side fets typical current limiting threshold load capacitance and/or diode reverse recovery spikes hard short detect and latch-off in1 or in2 in2 or in1 in1 or in2 in2 or in1 in1 in2 outputs tri-stated outputs tri-stated outputs operational (per input control condition) sf i out , active current limiting (see figure 7) i out , current (a) overcurrent minimum threshold t a t b 8.0 time i l o a d , o u t p u t c u r r e n t ( a ) typical pwm load current limiting waveform hard output short latch-off t a = tristate output off time t b = current limit blank time 6.5 hard short detect latch-off prevented during t b short circuit detect threshold t a = output latch-off time t b = output blanking time i scl short circuit detect threshold i out , current (a) typical current limiting waveform
analog integrated circuit device data 10 freescale semiconductor 33886 typical switching waveforms typical switching waveforms important for all plots, the following applies: ?ch2 = 2.0 a per division ?l load = 533 h @ 1.0 khz ?l load = 530 h @ 10.0 khz ?r load = 4.0 ? figure 10. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 1.0 khz, and duty cycle of 10% figure 11. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 1.0 khz, and duty cycle of 50% figure 12. output voltage and current vs. input voltage at v+ = 34 v, pmw frequency of 1.0 khz, and duty cycle of 90%, showing device in current limiting mode figure 13. output voltage and current vs. input voltage at v+ = 22 v, pmw frequency of 1.0 khz, and duty cycle of 90% v+=24 v f pwm =1.0 khz duty cycle=10% i out output voltage (out1) input voltage (in1) v+=24 v f pwm =1.0 khz duty cycle=50% i out output voltage (out1) input voltage (in1) v+=34 v f pwm =1.0 khz duty cycle=90% output voltage (out1) i out input voltage (in1) v+=22 v f pwm =1.0 khz duty cycle=90% i out output voltage (out1) input voltage (in1)
analog integrated circuit device data freescale semiconductor 11 33886 typical switching waveforms figure 14. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 10 khz, and duty cycle of 50% figure 15. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 10 khz, and duty cycle of 90% figure 16. output voltage and current vs. input voltage at v+ = 12 v, pmw frequency of 20 khz, and duty cycle of 50% for a purely resistive load figure 17. output voltage and current vs. input voltage at v+ = 12 v, pmw frequency of 20 khz, and duty cycle of 90% for a purely resistive load v+=24 v f pwm =10 khz duty cycle=50 % output voltage (out1) i out input voltage (in1) v+=24 v f pwm =10 khz duty cycle=90 % output voltage (out1) i out input voltage (in1) v+=12 v f pwm =20 khz duty cycle=50 % output voltage (out1) i out input voltage (in1) v+=12 v f pwm =20 khz duty cycle=90 % output voltage (out1) i out input voltage (in1)
analog integrated circuit device data 12 freescale semiconductor 33886 typical switching waveforms table 5. truth table the tri-state conditions and the fault status are reset using d1 or d2 . the truth table uses the following notations: l = low, h = high, x = high or low, and z = high impedance (all output power transistors are switched off). device state input conditions fault status flag output states d1 d2 in1 in2 fs out1 out2 forward l h h l h h l reverse l h l h h l h freewheeling low l h l l h l l freewheeling high l h h h h h h disable 1 (d1) h x x x l z z disable 2 ( d2 ) x l x x l z z in1 disconnected l h z x h h x in2 disconnected l h x z h x h d1 disconnected z x x x l z z d2 disconnected x z x x l z z undervoltage (28) x x x x l z z overtemperature (29) x x x x l z z short circuit (29) x x x x l z z notes 28. in the case of an undervoltage condition, the outputs tri-st ate and the fault status is set logic low. upon undervoltage rec overy, fault status is reset automatically or automatically cleared and the outputs are restored to their original operating condition. 29. when a short circuit or overtemperatur e condition is detected, the power outputs are tri-state latched-off independent of th e input signals and the fault status flag is set logic low.
analog integrated circuit device data freescale semiconductor 13 33886 electrical performance curves electrical per formance curves figure 18. typical high-side r ds(on) versus v+ figure 19. typical low-side r ds(on) versus v+ 5911 7131519 37 33 35 39 27 41 29 17 21 23 25 31 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 volts ohms 5911 7131519 37 33 35 39 27 41 29 17 21 23 25 31 0.13 0.128 0.126 0.124 0.122 0.12 ohms v pwr ohms volts
analog integrated circuit device data 14 freescale semiconductor 33886 electrical performance curves figure 20. typical quiescent supply current versus v+ 5911 7131519 37 33 35 39 27 41 29 17 21 23 25 31 5.0 4.0 3.0 2.0 1.0 0.0 ohms v pwr 6.0 7.0 8.0 9.0 milli amperes volts
analog integrated circuit device data freescale semiconductor 15 33886 functional description introduction functional description introduction numerous protection and operational features (speed, torque, direction, dynamic braking, and pwm control), in addition to the 5.0 a current capability, make the 33886 a very attractive, cost-effective solution for controlling a broad range of fractional horsepower dc motors. a pair of 33886 devices can be used to control bipolar stepper motors in both directions. in addition, the 33886 can be used to control permanent magnet solenoids in a push-pull variable force fashion using pwm control. the 33886 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding ac currents. as shown in figure 2 , simplified internal block diagram, page 2 , the 33886 is a fully prot ected monolithic h-bridge with fault status reporting. for a dc motor to run the input conditions need be as follows: d1 input logic low, d2 input logic high, fs flag cleared (logic high), with one in logic low and the other in logic high to define output polarity. the 33886 can execute dynamic braking by simultaneously turning on either both high-side mosfets or both low-side mosfets in the output h-bridge; e.g., in1 and in2 logic high or in1 and in2 logic low. the 33886 outputs are capable of providing a continuous dc load current of 5.0 a from a 40 v v+ source. an internal charge pump supports pwm frequencies up to 10 khz. an external pull-up resistor is required for the open drain fs pin for fault status reporting. two independent inputs (in1 and in2) provide control of the two totem-pole half-bridge ou tputs. two disable inputs (d1 and d2 ) are for forcing the h-bridge outputs to a high impedance state (all h-br idge switches off). the 33886 has undervoltage shutdown with automatic recovery, active current limiti ng, output short-circuit latch- off, and overtemperature latch-off. an undervoltage shutdown, output short circuit latch-off, or overtemperature latch-off fault condition will cause the outputs to turn off (i.e., become high impedance or tri-stated) and the fault output flag to be set low. either of the disable inputs or v+ must be ?toggled? to clear the fault flag. the short circuit / overtemperature shutdown scheme is unique and best described as using a junction temperature- dependent active current ?fold back? protection scheme. when a short circuit condition is experienced, the current limited output is ?ramped down? as the junction temperature increases above 160 c, until at 175 c the current has decreased to about 2.5 a. above 175 c, overtemperature shutdown (latch-off) occurs. this feature allows the device to remain in operation for a longer time with unexpected loads, while still retaining adequate protection for both the device and the load. functional pin description power/analog grounds (pgnd and agnd) power and analog ground pins. the power and analog ground pins should be connected together with a very low impedance connection. positive power supply (v+) v+ pins are the power supply inputs to the device. all v+ pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. v+ pins have an undervoltage threshold. if the supply voltage drops below a v+ undervoltage threshold, the output power stage switches to a tri-state condition and the fault status flag is set and the faul t status pin voltage switched to a logic low. when the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins and the fault stat us flag is automatically reset logic high. fault status ( fs ) this pin is the device fault stat us output. this output is an active low open drain structure requiring a pull-up resistor to 5.0 v. refer to table 5, truth table , page 12 . logic input 1, 2 and disable1, 2 (in1, in2, d1, and d2) these pins are input control pins used to control the outputs. these pins are 5.0 v cmos-compatible inputs with hysteresis. the in1 and in2 independently control out1 and out2, respectively. d1 and d2 are complimentary inputs used to tri-state disa ble the h-bridge outputs. when either d1 or d2 is set (d1 = logic high or d2 = logic low) in the disable state, outputs out1 and out2 are both tri-state disabled; however, the rest of the device circuitry is fully operational and the supply i q (standby) current is reduced to a few milliamperes. refer to table 5, truth table , and static electrical characteristics table, page 5 .
analog integrated circuit device data 16 freescale semiconductor 33886 functional description functional pin description h-bridge output 1, 2 (out1 and out2) these pins are the outputs of the h-bridge wit h integrated output fet body diodes. the bri dge output is controlled using the in1, in2, d1, and d2 inputs. the outputs have active current limiting above 6.5 a. t he outputs also have thermal shutdown (tri-state latch-off) with hysteresis as well as short circuit latch-off protection. a disable timer (time t b ) incorporated to detect currents that are higher than active cu rrent limit is activated at each output activation to facilitate detecting hard output short conditions (see figure 9 , page 9 ). charge pump capacitor (ccp) charge pump output pin. a fi lter capacitor (up to 33 nf) can be connected from the c cp pin and pgnd. the device can operate without the external capacitor, although the c cp capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and pwm frequency.
analog integrated circuit device data freescale semiconductor 17 33886 functional device operation functional pin description functional device operation short circuit protection if an output short circuit condition is detected, the power outputs tri-state (latch-off) independent of the input (in1 and in2) states, and the fault status output flag is set logic low. if the d1 input changes from logic high to logic low, or if the d2 input changes from logic low to logic high, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic high state. the output stage will always switch into the mode defined by the input pins (in1, in2, d1, and d2 ), provided the device junction temperature is wit hin the specified operating temperature. active current limiting the maximum current flow under normal operating conditions is internally limited to i lim (5.2 a to 7.8 a). when the maximum current value is re ached, the output stages are tri-stated for a fixed time (t a ) of 20 s typical. depending on the time constant associated wit h the load characteristics, the current decreases during the tr i-state duration until the next output on cycle occurs (see figures 9 and 12 , page 9 and page 10 , respectively). the current limiting threshold value is dependent upon the device junction temperature. when -40 c < t j < 160 c, i lim is between 5.2 a and 7.8 a. when t j exceeds 160 c, the i lim current decreases linearly down to 2.5 a typical at 175 c. above 175 c the device overtemperature circuit detects t lim and overtemperature shutdown occurs (see figure 7 , page 8 ). this feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160 c. overtemperature shutdown and hysteresis if an overtemperature condit ion occurs, the power outputs are tri-state (latched-off) independent of the input signals and the fault status flag is set logic low. to reset from this condition , d1 must change from logic high to logic low, or d2 must change from logic low to logic high. when reset, the output stage switches on again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. note resetting from the fault condition will clear the fault status flag. main differences compared to mc33186dh1 ? cod pin has been removed. pin 8 is now a do not connect (dnc) pin. ? pin 20 is no longer connected in the 20 hsop package. it is now a dnc pin. ?r ds(on) max at t j = 150c is now 225 m ? per each output transistor. ? maximum temperature opera tion is now 160c, as minimum thermal shutdown temperature has increased. ? current regulation limiting foldback is implemented above 160c t j . ? thermal resistance junction to case has been increased from ~2.0c/w to ~5.0c/w.
analog integrated circuit device data 18 freescale semiconductor 33886 functional device operation performance performance the 33886 is designed for enhanced thermal performance. the significant f eature of this device is the exposed copper pad on which the power die is soldered. this pad is soldered on a pcb to provide heat flow to ambient and also to provide thermal capacitance. the more copper area on the pcb, the better the pow er dissipation and transient behavior will be. example characterization on a double-sided pcb: bottom side area of copper is 7.8 cm 2 ; top surface is 2.7 cm 2 (see figure 21 ); grid array of 24 vias 0.3 mm in diameter. figure 21. pcb test layout figure 22 shows the thermal response with the device soldered on to the test pcb described in figure 21 . figure 22. 33886 thermal response top side bottom side 0,1 1 10 100 0,001 0,01 0,1 1 10 100 1000 10000 t, time (s) rth (c/w)
analog integrated circuit device data freescale semiconductor 19 33886 typical applications typical applications a typical application schematic is shown in figure 23 . for precision high-current applic ations in harsh, noisy environments, the v+ by-pass capacitor may need to be substantially larger. figure 23. 33886 typical application schematic motor agnd out1 pgnd v+ c cp out2 d2 d1 fs in1 in2 33 nf 47 f v+ 33886 + in2 in1 fs d1 d2 dc
analog integrated circuit device data 20 freescale semiconductor 33886 packaging package dimensions packaging package dimensions important for the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ash70702a listed below. seating plane datum plane bottom view a x 45 e1 e d h e 18x b m bbb c 20 11 10 1 e2 notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per asme y14.5m, 1994. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. dimensions d and e1 do not include mold protrusion. allowable protrusion is 0.150 per side. dimensions d and e1 do include mold mismatch and are determined at datum plane ?h?. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. 6. datums ?a? and ?b? to be determined at datum plane ?h?. 7. dimension d does not include tiebar protrusions. allowable tiebar protrusions are 0.150 per side. d2 d1 e3 ??? ??? a m aaa c exposed heatsink area a b c h pin one id 10x y gauge plane detail y (1.600) l w w bbb c l1 a1 a3 dim min max millimeters a 3.000 3.400 a1 0.100 0.300 a2 2.900 3.100 a3 0.00 0.100 d 15.800 16.000 d1 11.700 12.600 d2 0.900 1.100 e 13.950 14.450 e1 10.900 11.100 e2 2.500 2.700 e3 6.400 7.200 e4 2.700 2.900 l 0.840 1.100 l1 0.350 bsc b 0.400 0.520 b1 0.400 0.482 c 0.230 0.320 c1 0.230 0.280 e 1.270 bsc h ??? 1.100 0 8 aaa 0.200 bbb 0.100 e/2 dh suffix vw (pb-free) suffix 20-pin hsop plastic package 98ash70702a issue a
analog integrated circuit device data freescale semiconductor 21 33886 5.0 a h-bridge thermal addendum - revision 2.0 5.0 a h-bridge thermal addendum - revision 2.0 introduction this thermal addendum is provid ed as a supplement to the mc33186 technical data sheet. the addendum provi des thermal performance information that may be critical in the design and devel opment of system a pplications. all electrical, application, and packaging in formation is provided in the data sheet. packaging and thermal considerations the mc33186 is offered in a 20 pin hsop exposed pad, single die package. there is a single heat source (p), a single junction temperature (t j ), and thermal resistance (r ja ). the stated values are solely for a thermal performance comparison of one package to another in a standardized en vironment. this methodology is not meant to and will not predict the perfor mance of a package in an application- specific environment. stated values were obtained by measurement and simulation according to the standards listed below. standards notes: 1.per jedec jesd51-2 at natural convection, still air condition. 2.2s2p thermal test board per jedec jesd51-5 and jesd51-7. 3.per jedec jesd51-8, with the board temperature on the center trace near the center lead. 4.single layer thermal test board per jedec jesd51-3 and jesd51-5. 5.thermal resistance between the die junction and the exposed pad surface; cold plate attached to the package bottom side, remaining surfaces insulated. figure 24. thermal land pattern for direct thermal attachment according to jesd51-5 20-pin hsop-ep 33886 note for package dimensions, refer to the 33886 device data sheet. dh suffix vw (pb-free) suffix 98ash70702a 20-pin hsop-ep t j = r ja . p table 6. thermal performance comparison thermal resistance [ c/w] r ja (1) (2) 20 r jb (2) (3) 6.0 r ja (1) (4) 52 r jc (5) 1.0 1.0 1.0 0.2 0.2 soldermast openings thermal vias connected to top buried plane * all measurements are in millimeters 20 terminal hsop-ep 1.27 mm pitch 16.0 mm x 11.0 mm body 12.2 mm x 6.9 mm exposed pad
analog integrated circuit device data 22 freescale semiconductor 33886 5.0 a h-bridge thermal addendum - revision 2.0 figure 25. thermal test board device on thermal test board r ja is the thermal resistance between die junction and ambient air. r js is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package (see figure 25 ). 20-pin hsop 1.27 mm pitch 16.0 mm x 11.0 mm body 12.2 mm x 6.9 mm exposed pad dnc agnd in2 d1 c cp v+ out2 out2 d2 pgnd pgnd fs v+ out1 out1 dnc pgnd pgnd in1 v+ 1 2 3 4 5 6 7 8 9 10 20 19 16 15 14 13 12 11 18 17 33886 pin connections a material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a : cu heat-spreading areas on board surface ambient conditions: natural convection, still air table 7. thermal resistance performance thermal resistance area a (mm 2 ) c/w r ja 0.0 52 300 36 600 32 r js 0.0 10 300 7.0 600 6.0
analog integrated circuit device data freescale semiconductor 23 33886 5.0 a h-bridge thermal addendum - revision 2.0 figure 26. device on thermal test board r ja figure 27. transient thermal resistance r ja device on thermal test board area a = 600 (mm 2 ) 0 10 20 30 40 50 60 heat spreading area a [mm2] thermal resistance [oc/w ] 0 300 600 x r ja 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 time[s] thermal resistance [oc/w] time(s) x r ja
analog integrated circuit device data 24 freescale semiconductor 33886 revision history revision history revision date description of changes 7.0 7/2005 ? implemented revision history page ? added thermal addendum ? converted to freescale format 8.0 2/2007 ? updated data sheet format ? removed peak package reflow temperature duri ng reflow (solder reflow) parameter from maximum ratings on page 4 . added note with instructions to obtain this information from www.freescale.com.
mc33886 rev 8.0 2/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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